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a u s t ri a m i c r o s y s t e m s
AS1504, AS1505
O c ta l 8 - B i t P r o g r a m m a b l e L o w - P o w e r D A C s w i t h S h u td o w n a n d M i d - S c a l e R e s e t
D a ta S he e t
1 General Description
The AS1504/AS1505 are low-power (5A @ 5V) individually programmable 8-channel, 8-bit resolution digital-toanalog converters. All eight DACs share a common reference-voltage input making them ideal for applications where adjustments start at a nominal voltage. Table 1. Standard Products Model AS1504 AS1505 Functionality Mid-Scale Reset Pin Separate VREFL Range Settings
2 Key Features
! ! ! ! ! ! ! ! !
8 Individually-Controlled DACs Replaces 8 Potentiometers Standard 3-Wire Serial Interface Single-Supply Operation: +3 to +5V Mid-Scale Reset Pin (AS1504) Separate VREFL Range Setting (AS1505) Shutdown Mode: 25W (IDD and IREF) Power-On Reset 16-pin SOIC-150 Package
The devices feature a low-power shutdown reference input current (5A) that enables the devices to maintain individual DAC latch settings during shutdown until normal operation is resumed. The devices are controlled via a standard 3-wire serial interface. Data is shifted into the DACs via the internal serial-to-parallel shift register. The AS1504/AS1505 are available in a 16-pin SOIC-150 package.
3 Applications
The devices are ideal for video amplifier gain control, video equipment voltage-controlled frequencies and bandwidths, CRT display geometric corrections and automatic adjustments, or any other space-limited DAC application with low power-consumption requirements.
Figure 1. Block Diagram
VREFH VREFH DAC1 VOUT VREFL
VREFL AS1505 Only
8-Bit Latch CK RSN DAC 1 Select 8 Address 3 11-Bit Serial Latch 8 D CK RSN
OUT1
8
VDD
GND
SDI CLK
CSN
8-Bit Latch CK RSN
AS1504/ AS1505
RSN AS1504 Only
VREFH DAC8 VOUT VREFL 8
OUT8
SHDNN
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4 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 3 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter VDD to GND VREFH and VREFH to GND OUTx to GND Digital Input Voltage to GND Package Power Dissipation Operating Temperature Range Storage Temperature Range Maximum Junction Temperature (TJ Max) Thermal Resistance (JA) Electro-Static Discharge -40 -65 +85 +150 +150 60 <1 C C C C/W kV The reflow peak soldering temperature (body temperature) specified is in compliance with IPC/JEDEC J-STD-020C "Moisture/ Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". Min -0.3 0 0 0 Max +7 VDD VDD VDD Units V V V V TJ Max - TAMB/JA Comments
Package Body Temperature
+260
C
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5 Electrical Characteristics
VDD = +3.0V 10% or +5.0V 10%, VREFH = VDD, VREFL = 0V, -40C TAMB +85C (unless otherwise specified). Table 3. Electrical Characteristics Symbol N INL DNL GFSE VZSE ROUT R/ROUT Parameter Resolution Integral Non-Linearity Error Differential Non-Linerarity Full-Scale Error Zero-Code Error DAC Output Resistance Output Resistance Match High Voltage 2 Input Range Low Voltage Input Range 3 (AS1505 Only) Input Resistance
4 1
Conditions
Min 8 -0.75
Typ
Max
Unit Bit
Static Accuracy (specifications apply to all DACs) 0.15 +0.75 0.1 0.2 0.1 5 1 +0.5 +1 +0.5 8 LSB LSB LSB LSB k %
Guaranteed Monotonic
-0.5 -1 -0.5 3
Reference Input VREFH VREFL RIN CREFH CREFL Digital Inputs VIH VIL IIL CIL Logic High Logic Low Input Current Input Capacitance
6 5
0 0 Digital Inputs = 55h, VREFH VDD Digital Inputs = All 0s Digital Inputs = All 1s 625 60 60
VDD VDD
V V pF pF
High Reference Input 5 Capacitance Low Reference Input 5 Capacitance
VDD = +5V VDD = +3V VDD = +5V VDD = +3V VIN = 0 or +5V
2.4 2.1 0.8 0.6 1 5
V V A pF
Power Supplies VDDRANGE
Power Supply Range Supply Current (CMOS) Supply Current (TTL) Shutdown Current Power Dissipation Power Supply Rejection Ratio
5
2.7 VIH = VDD or VIL = 0V VIH = 2.4V or VIL = 0.8V, VDD = +5.5V SHDNN = 0V VIH = VDD or VIL = 0V, VDD = +5.5V VDD = +5V 10%, VREFH = +4.5V VDD = +3V 10%, VREFH = +2.7V 0.01 0.01 1 0.01
5.5 5 4 5 27.5 0.001 0.002
V A mA A W %/%
IDD
IREFH PDISS PSRR
Dynamic Performance tS CT
Positive or Negative VOUT Settling Time Crosstalk
7
0.5 LSB Error Band
0.5 90
s dB
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Table 3. Electrical Characteristics (Continued) Symbol Parameter
5, 8
Conditions
Min
Typ
1
Max
Unit
Switching Characteristics tCH tCL tDS tDH tCSS tCSW tRS tCSH tCS1
Input Clock Pulse Width Data Setup Time Data Hold Time CSN Setup Time CSN High Pulse Width Reset Pulse Width CLK-Rise to CSN-Rise Hold Time CSN-Rise to Next Rising Clock Time
High Clock Level Low Clock Level
15 15 5 5 10 10 60 15 10
ns ns ns ns ns ns ns ns ns
1. Typ values are average readings at +25C. 2. VREFH can be any value between VDD and GND. 3. VREFL can be any value between VDD and GND. 4. With all DACs set to code 0x55h. Typical input resistance per DAC is 5kOhm with code 0x55h. 5. Guaranteed by design; not subject to production test. 6. VIN = 0V or VDD (CMOS); DAC outputs unloaded. PDISS is calculated as IDD x VDD. 7. Measured at an OUTx pin where an adjacent OUTx pin is making a full-scale voltage change. 8. See Figure 13 on page 9 for location of measured values. All input control voltages are specified with tR = tF = 2ns.
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6 Typical Operating Characteristics
Figure 2. Differential Non-Linearity; VDD = 2.7V, VREFH = 2.7V, VREFL= 0V, TAMB = -40, +25, and +85C
0.6 0.4
Figure 3. Integral Non-Linearity; VDD = 2.7V, VREFH = 2.7V, VREFL= 0V, TAMB = -40, +25, and +85C
0.6 0.4
DNL (LSB) .
0 -0.2 -0.4 -0.6 0 32 64 96 128 160 192 224 256
INL (LSB) .
0.2
0.2 0 -0.2 -0.4 -0.6 0 32 64 96 128 160 192 224 256
Code
Figure 4. Reference Current vs. Code; VDD = 2.7V, VREFH = 2.7V, VREFL= 0V
500
Code
Figure 5. Reference Current vs. Code; VDD = 5.5V, VREFH = 5.5V, VREFL= 0VReference C.
1250
400
1000
IREF per DAC (A) .
300
IREF per DAC (A) .
0 32 64 96 128 160 192 224 256
750
200
500
100
250
0
0 0 32 64 96 128 160 192 224 256
Code
Figure 6. DNL vs. Channel; VDD = 2.7V, T = 25C
0.2
MAX
Code
Figure 7. Offset Error vs. Channel; VDD = 2.7V, T = 25C, all DACs (except selected) = 0x00h
0.0002
Offset Error (LSB))
0.1
Offset Error (LSB))
MIN
-0.1 0 1 2 3
0 0
0.00005
0
0.0001
0.00015
4
5
6
7
8
1
2
3
4
5
6
7
8
Channel
Channel
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Data Sheet
Figure 8. Gain Error vs. Channel; Figure 9. Output Resistance vs. Channel; VDD = 2.7V, T = 25C, all DACs (except selected) = 0x00h VDD = 2.7V, T = 25C, all DACs (except selected) = 0x00h
0.3 5600
Output Resistance (Ohm).
0 1 2 3 4 5 6 7 8
5580
Gain Error (LSB) .
0.2
5560
5540
0.1
5520
0
5500 0 1 2 3 4 5 6 7 8
Channel
Channel
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Pin Assignments
Data Sheet
7 Pinout
Pin Assignments
Figure 10. Pin Assignments (Top View)
VREFH OUT1 OUT2 OUT3 OUT4 SHDNN CSN GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD RSN OUT8 OUT7 OUT6 OUT5 SDI CLK
VREFH OUT1 OUT2 OUT3 OUT4 SHDNN CSN GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD OUT8 OUT7 OUT6 OUT5 SDI CLK VREFL
AS1504
AS1505
Pin Descriptions
Table 4. Pin Descriptions Pin Number Pin Name Description Serial Clock Input. Positive-edge triggered. Chip Select. When this active-low pin goes high, the serial input register data is decoded based on the address bits and loaded into the target DAC register. Ground DAC 1 Output. DAC 1 address = 0002. DAC 2 Output. DAC 1 address = 0012. DAC 3 Output. DAC 1 address = 0102. DAC 4 Output. DAC 1 address = 0112. DAC 5 Output. DAC 1 address = 1002. DAC 6 Output. DAC 1 address = 1012. DAC 7 Output. DAC 1 address = 1102. DAC 8 Output. DAC 1 address = 1112. Reset (AS1504 Only). Active-low asynchronous reset to mid-scale output setting. Loads all DAC latches with 80h. Serial Data Input Shutdown. Active-low reference input open-circuit. All DAC outputs open-circuit. Note: DAC latch settings are maintained during shutdown. Positive Supply Voltage. +3 to +5V. Common High-Side DAC Reference Input Common Low-Side DAC Reference Input (AS1505 Only).
CLK CSN GND OUT1 OUT2 OUT3 OUT4 OUT5 (see Figure 10) OUT6 OUT7 OUT8 RSN SDI SHDNN VDD VREFH VREFL
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Data Sheet
8 Detailed Description
The AS1504/AS1505 contain eight DAC channels of programmable voltage output adjustment capability. OUTx can be individually changed in random sequence. The fast serial-data loading (33MHz) allows all eight DACs to be quickly loaded (3ms typ; 12 x 8 x 30ns).
Figure 11. Detailed Block Diagram
CSN D7 D6 D5 D4 DAC1 D3 Register D2 D1 D0 R VREFH
CLK D10 D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 Serial Register
EN Address Decode
DAC1 OUT1 8
D SDI
8
D7 D6 D5 D4 DAC8 D3 Register D2 D1 D0 R
DAC1 OUT8 8
SHDNN RSN AS1504 Only
AS1504/ AS1505
VREFL AS1505 Only
Each output voltage can be programmed by clocking an 11-bit serial data word into pin SDI (see Figure 12). The format of this data word is three address bits (MSB first, followed by eight data bits (see Table 5)). To determine which of the DAC registers is to receive the serial register data (bits B7:B0) the DACx address is decoded as:
DACx = A2 x 4 + A1 x 2 + A0 + 1 Figure 12. Timing Diagram
SDI 1 A2 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 DO
(EQ 1)
CLK
1 0 1 0 DAC Register Load
CSN
VOUT
+5V 0V
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Data Sheet
Table 5. AS1504/AS1505 Serial Data Word Format Address Bits B10 B9 B8 B7 B6 B5 Data Bits B4 B3 B2 B1 B0
A2 MSB 2
10
A1
9
A0 LSB
8
D7 MSB 2
7
D6
6
D5
5
D4
4
D3
3
D2
2
D1
1
D0 LSB
0
2
2
2
2
2
2
2
2
2
The AS1504 provides a mid-scale reset activated by pin RSN which simplifies settings on initial power up. The AS1505 has a high- and low-side reference (pins VREFH and VREFL) to determine independent positive full-scale and zero-scale settings to optimize resolution. Both devices feature a power-on reset which resets them to mid-scale. Both models feature a low-power shutdown mode which places the device into low power-consumption mode resulting in only leakage currents being consumed from the power supply, VREFx inputs, and all 8 outputs. In shutdown mode the DACx latch settings are maintained. When returning to normal operation from shutdown mode, the DACx outputs return to their previous voltage settings.
Figure 13. Serial Data Input Timing Diagram; RSN = 1
1 SDI 0 Ax or Dx Ax or Dx tDS tCH 1 CLK 0 tCSS 1 CSN 0 tS VOUT +5V 0V 1 LSB 1 LSB Error Band tCSW tCL tCSH tDH tCS1
Figure 14. Reset Timing Diagram
tRS 1 RSN 0 tS +5V VOUT +2.5V 1 LSB Error Band 1 LSB
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Programming The Output Voltage
Data Sheet
Figure 15. Equivalent DAC Circuit
To other DACs P CH VREFH N CH MSB 2R Ox
DAC Register D7 D6 D0 2R
R
R
LSB
2R
GND VREFL
2R
Programming The Output Voltage
The output voltage range is determined by the external reference connected to pins VREFH and VREFL (see Figure 15 on page 10 for a simplified diagram of the equivalent DAC circuit). VREFL for the AS1504 is internally connected to GND and therefore cannot be offset. Pin VREFH can be tied to VDD and pin VREFL can be tied to GND establishing a basic rail-to-rail output voltage programming range. Other output ranges are established by the use of different external voltage references. The programmed output voltage is determined as:
VOUT (Dx) = (Dx)/256 x (VREFH - VREFL) + VREFL Where: (EQ 2)
Dx is the data contained in the 8-bit DACx latch. For example, when VREFH = +5V and VREFL = 0V the output voltages will be generated per the codes listed in Table 6.
Table 6. Output Voltages Data Bits VOUTx Output State (VREFH = +5V, VREFL = 0V)
255 128 1 0
4.98V 2.50V 0.02V 0.00V
Full-Scale Half-Scale (Mid-Scale Reset Value) 1 LSB Zero-Scale
Reference Inputs
The reference input pins (VREFH and VREFL) set the output voltage range of all eight DACs. For the AS1504, only pin VREFH is available to establish a programmable full-scale output voltage.
Note: The external reference voltage can be any value between 0 and VDD but must not exceed VDD.
The AS1505 uses pin VREFL to establish the zero-scale output voltage. Any voltage can be applied between 0 and VDD. VREFL can be smaller or larger than VREFH since the DAC design uses fully bi-directional switches as shown in Figure 15. The input resistance to the DAC has a code dependent variation that has a nominal worst case measured at 55h, which is approximately 2k. When VREFH is greater than VREFL, the REFL reference must be able to sink current out of the DAC ladder, while the REFH reference is sourcing current into the DAC ladder. The DAC design minimizes reference glitch current, thus maintaining minimum interference between DAC channels during code changes.
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DAC Outputs
Data Sheet
DAC Outputs
The 8 DAC outputs (OUT1:OUT8) present a constant output resistance of approximately 5k independent of code settings. The distribution of ROUT from DAC to DAC typically matches within 1%. Device-to-device matching is processlot dependent with a 20% variation. The change in ROUT with temperature has a 500 ppm/C temperature coefficient.
Note: During shutdown the OUTx outputs are open-circuited.
Serial Interface
The AS1504/AS1505 are controlled via a standard three-wire serial input. The three input pins are CLK, CSN and SDI. The positive-edge sensitive CLK input requires a clean transition to avoid clocking spurious data into the serial input register (standard logic families are perfectly adequate). If mechanical switches are used for device evaluation, they should be de-bounced by a flip-flop or other suitable means. Figure 11 on page 8 shows details of the internal digital circuitry. When CSN is pulled low, the clock can load data into the serial register on each positive clock edge (see Table 7).
Table 7. Function of Pins CSN and CLK CSN CLK Register Activity
1 0 Positive Edge
X
No effect. Data is transferred from the serial register to the decoded DAC register (see Figure 16).
Positive Edge Shifts serial register one bit loading the next bit in from the SDI pin. X
The data setup and data hold times in Table 3 on page 3 determine the valid data time requirements. The last 11 bits of the data word entered into the serial register are held when CSN goes high. When CSN goes high it gates the address decoder which enables one of the eight positive-edge triggered DAC registers (see Figure 16).
Figure 16. Equivalent Control Logic
AS1504/ AS1505
CSN
Address Decode
DAC1 DAC2 DAC8
CLK SDI
Serial Register
The target DAC register is loaded with the last eight bits of the serial data word completing one DAC update. To change all eight output settings, eight separate 11-bit data words must be clocked in to the device.
Note: All digital inputs (CSN, SDI, RSN, SHDNN, and CLK) are protected with the series input resistor and parallel zener diode ESD circuit illustrated in Figure 17. Figure 17. Equivalent ESD Protection Circuit
50
Logic
Note: Digital inputs can be driven by voltages exceeding VDD thus providing logic level translation from 5V logic when the device is operated from a 3V supply.
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Supply Bypassing
Data Sheet
9 Application Information
Supply Bypassing
The AS1504/AS1505 require a well-filtered power source. In most applications, the AS1504/AS1505 should be powered directly from the system power supply (+3 to +5V). However, if the logic supply is a switch-mode design, it will probably generate noise in the 20kHz to 1MHz range. Additionally, fast logic gates can generate transients hundred of millivolts in amplitude from wiring resistance and inductance. The circuit shown in Figure 18 isolates the analog section from any logic switching transients. Even if a separate power supply trace is not available, adequate supply bypassing will reduce supply-line induced errors. Local supply bypassing consisting of a 10F tantalum electrolytic capacitor in parallel with a 0.1F ceramic capacitor is recommended (see Figure 19).
Figure 18. Power Supply Traces
CMOS/TTL Logic Circuits
+
10F Tantalum
0.1F
AS1504/ AS1505
+5V Power Supply
Figure 19. Recommended Supply Bypassing
+5V
16
VDD
+
10F Tantalum
0.1F
AS1504/ AS1505
8
GND
Output Buffering
For most designs, the nominal 5k output impedance of the AS1504/AS1505 is sufficient to drive succeeding circuitry. If a lower output impedance is required, an external amplifier can be added (see Figure 20 on page 13). A single amplifier should be used as a simple buffer to reduce the output resistance of DAC1. An amplifier with low offset voltage, low supply current, and operation at less than 3V is recommended due to its rail-to-rail input and output operation. DAC2 and DAC3 are configured in a summing arrangement where DAC3 provides the coarse output voltage setting and DAC2 is used for fine adjustments. The use of R1 in series with DAC2 (see Figure 20 on page 13)attenuates its contribution to the voltage sum node at the output of DAC3.
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Increasing Output Voltage Swing
Data Sheet
Figure 20. Output Buffering
+5V
VREFH
VDD Amplifier VH VL DAC1 + - VH DAC2 VL VH DAC3 VL R1 100k + - Summer Circuit with Fine Trim Adjustment Simple Buffer 0 to 5V
AS1504/ AS1505
VREFL GND
Increasing Output Voltage Swing
An external amplifier can be used to extend the output voltage swing beyond the power supply rails of the AS1504/ AS1505. This design allows for a simple digital interface to the DAC, while expanding the output swing to take advantage of higher voltage external power supplies (e.g., DAC 1 of Figure 21 is configured to swing from -5 to +5V). The actual output voltage is given by:
VOUT = (1+ (RF/RS))((D/256)5V) - 5V Where: (EQ 3)
D is the DAC input value (i.e., 0 to 255). This design can be combined with the circuit in Figure 20 if very accurate adjustments around 0V are required.
Figure 21. Increasing Output Voltage Swing
+5V RS 100k RF 100k
VDD
VREFH -
+5V -5 to +4.98V
DAC1 OUT1
+ -5V +12V OUT2 VREFL AS1505 Only + 0 to +10V -
AS1504/ AS1505
DAC2
GND
100k 100k
DAC 2 (non-inverting AV = 2 configuration) of Figure 21 increases the available output swing to +10V. The feedback resistors can be adjusted to provide scaling of the output voltage, within the limits of the external operational amplifier power supplies.
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Microprocessor Interfaces
Data Sheet
Microprocessor Interfaces
The AS1504/AS1505 serial interface provides a simple connection to a wide range of microprocessors, most of which have built-in serial data capability that can be used for communicating with the device.
Note: In cases where a serial port is not available on the microprocessor, the AS1504/AS1505 can be addressed via software.
Eleven data bits are required to load data into the AS1504/AS1505 (3 bits for the DAC address and 8 bits for the DAC value). If more than eleven bits are transmitted before the microprocessor chip select input goes high, the most-significant bits are ignored. Because most microprocessors transmit data in 8-bit words, it will need to send 16 bits to the AS1504/AS1505; however, the AS1504/AS1505 only responds to the last 11 bits clocked into the SDI input, so the serial data interface is not affected.
8051 Microprocessor Interface
Figure 22 shows the AS1504/AS1505 interface to an 8051 microprocessor. This interface uses the 8051 internal serial port as a simple 8-bit shift register (Mode 0 operation). 8051 Port3.0 serves as the serial data output port and Port3.1 serves as the serial clock.
Figure 22. AS1504-to-8051 Microprocessor Interface
+5V
VDD Serial Data Shift Register Shift Clock RX Port3.0 SDI TX Port3.1 CLK Port1.3 RSN
VREFH
0.1F
+
10F Tantalum
OUT1
AS1504
8051
Port1.2 SHDNN Port1.1 CSN 1.3 1.2 1.1 OUT8
Port 1
As data is written to the serial buffer register (SBUF, at Special Function Register location 99h), the data is automatically converted to serial format and clocked out via Port3.0 and Port3.1. Once 8 bits have been transmitted, the transmit interrupt flag (SCON.1) is set and the next 8 bits can be transmitted. The AS1504/AS1505 requires that CSN goes low at the start of the serial data transfer. Additionally, pin CLK must be high when CSN goes high at the end of each data transfer. The 8051 serial clock meets these requirements, since Port3.1 begins and ends the serial data transfer in a high state.
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Data Sheet
10 Package Drawings and Markings
The AS1504/AS1505 is available in a 16-pin SOIC-150 package.
Figure 23. 16-pin SOIC-150 Package
Notes:
1. Lead coplanarity should be 0 to 0.10mm (.004") max. 2. Package surface finishing: - Top, matte (charmilles #18-30) - All sides, matte (charmilles +18-30) - Bottom, smooth or matte (charmilles +18-30) 3. All dimensions excluding mold flashes and end flash from the package body shall not exceed 0.25mm (.010") per side. 4. Details of pin #1 mark are optional but must be located within the area indicated.
Symbol A A1 A2 B C D E e H h L ZD
Min Max 1.52 1.72 0.10 0.25 1.37 1.57 0.36 0.46 0.19 0.25 9.80 9.98 3.81 3.99 1.27BSC 5.80 6.20 0.25 0.50 0.41 1.27 0 8 0.51 REF
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Data Sheet
11 Ordering Information
The devices are available as the standard products shown in Table 8.
Table 8. Ordering Information Model Description Delivery Form Package
AS1504-T AS1505-T
Octal 8-Bit DAC, Mid-Scale Reset Octal 8-Bit DAC, Separate VREFL Range Settings
Tape and Reel Tape and Reel
16-pin SOIC-150 Narrow 16-pin SOIC-150 Narrow
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Data Sheet
Copyrights
Copyright (c) 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 e-mail: info@austriamicrosystems.com For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com
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